1. Field of the Invention
This invention is related to the protection of integrated circuits on a semiconductor substrate from voltage overstress due to pulses resulting from electrostatic discharge (ESD). More particularly, this invention is related to semiconductor devices and structures for improved protection of the integrated circuits.
2. Description of the Related Art
In FIG. 1a the N-channel metal oxide semiconductor (NMOS) field effect transistor (FET) 100 of the prior art is shown in an application, wherein it is configured as an ESD protection circuit. The drain of the NMOS FET 100 is connected to the input pad 115, the drain of the P-channel Metal Oxide Semiconductor (PMOS) FET 200, and to the internal circuits 110. The source and the gate of the PMOS FET 200 are connected to the voltage supply VDD. The source and gate of the PMOS FET 100 are connected to the substrate biasing voltage source Vss. The collectors of the parasitic bipolar junction transistors (BJT""s) 140a, 140b, 140c, 140d are structurally the drain of the NMOS FET 100. The emitters of the parasitic BJT""s 140a, 140b, 140c, 140d are structurally the source of the NMOS FET 100 which is connected to the substrate biasing voltage source Vss. The bases of the parasitic BJT""s 140a, 140b, 140c, 140d are structurally the channel region of the NMOS FET 100 are connected to the parasitic resistors 145a, 145b, 145c, 145d that is formed by the bulk resistance of the semiconductor substrate. The parasitic resistors 145a, 145b, 145c, 145d, and 150a, 150b, 150c, 150d form a resistive network connected to the ground reference.
A positive ESD source 120 such as the human body or electrostatically charged machinery is momentarily coupled to the input/output pad 115. The magnitude of a voltage pulse of the ESD source 120 is on the order of 1,000 volts or larger. As the voltage of the ESD source 120 is transferred through the metal connections to the drain of the NMOS FET 100, the gate to drain voltage of the NMOS FET 100 is exceeds the breakdown voltage. The drain to the substrate junction starts to enter the avalanche breakdown condition and then starts to generate large amounts of electronxe2x80x94hole pairs. The holes pass through the substrate bulk resistances 145a, 145b, 145c, 145d, and 150a, 150b, 150c, 150d. The voltage drop across the substrate bulk resistances 145a, 145b, 145c, 145d, and 150a, 150b, 150c, 150d forward bias the source to substrate junction, causing it to emit electrons. This condition starts the parasitic BJT""s 140a, 140b, 140c, 140d conducting. The substrate bulk resistances, 145a, 145b, 145c, 145d, and 150a, 150b, 150c, 150d are configured such that the base current of parasitic BJTs 140a and 140b are much larger than the base current of BJT""s 140c and 140d. Since the base currents are directly related to the collector currents until the parasitic BJT""s reach saturation, the currents of the parasitic BJT""s 140a and 140b are much greater than the collector currents of the parasitic 140c and 140d. This differential of the collector currents commonly called current crowding can cause BJT""s 140a and 140b to fail due to excessive current.
FIGS. 1b and 1c illustrate the top surface and cross-section of the NMOS FET 100 of FIG. 1a. A P-type material is implanted to a low concentration into the surface of the semiconductor substrate 200 to form the P-well 205. The P-well 205 forms an expitaxial area that is connected to the substrate biasing voltage source Vss. An N-type material is implanted to a high concentration to form the drain regions 210a, 210b, 210c, 210d of the NMOS FET 100. The N-type material is simultaneously implanted to a high concentration to form the source regions 215a, 215b, 215c of the NMOS FET 100.
The N-type material is further implanted to a very high concentration within the drain regions 210a, 210b, 210c, 210d and the source regions 215a, 215b, 215c, to form respectively low resistivity drain contact points 220a, 220b, 220c, 220d and low resistivity source contact points 225a, 225b, 225c. 
An insulating material is deposited on the surface of the semiconductor substrate 200 in the channel regions 260a, 260b, 260c, 260d, 260e, 260f to form a gate oxide 265a, 265b, 265c, 265d, 265e, 265f. Above the gate oxide 265a, 265b, 265c, 265d, 265e, 265f a conductive material such as highly doped polycrystalline silicon is deposited to form the gates 230a, 230b, 230c, 230d, 230e, 230f of the NMOS FET 100.
A second conductive material such as a aluminum is then deposited on the surface of the semiconductor substrate 200 to form the connecting lands 240 that connect the drain regions 210a, 210b, 210c, 210d to the input/output pad and the internal circuits through the low resistivity drain contacts 220a, 220b, 220c, 220d. Simultaneously, the second conductive material is also deposited on the surface of the semiconductor substrate 200 to form the connecting lands 245 from the source regions 215a, 215b, 215c to the substrate biasing source Vss through the low resistivity source contacts 225a, 225b, 225c. 
The first conductive material is further deposited to form the connecting land 250 that connects the gates 230a, 230b, 230c, 230d, 230e, 230f to the substrate biasing voltage source Vss.
As above described, when an ESD voltage source 120 of FIG. 1a is coupled to the input/output pad 115, the current crowding that results from nonuniform currents can cause the damage 270 shown.
U.S. Pat. No. 5,237,395 (Lee) describes an electrostatic discharge (ESD) protection circuit for protecting internal devices of an integrated circuit. The ESD protection circuit of Lee is coupled between the power rails of the integrated circuits. First and second current shunt paths between the power rails are maintained nonconductive during normal circuit operation. The ESD protection circuit of Lee causes the first and second current shunt paths to be triggered to a conductive mode in response to an ESD event on the power rails. A triggering circuit to trigger the first and second shunt paths employs a logic gate such as an inverter. The input of the inverter is coupled to the positive power rails and will maintain a low level output during normal operation. The inverter provides a high output in response to an ESD event on the power rail to trigger the first and second shunt paths.
U.S. Pat. No. 5,532,178 (Liaw et al.) teaches an improved process and integrated circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate with an NMOS electrostatic discharge circuit. The NMOS ESD circuit is formed in a P well on the substrate. The improvement includes an ESD NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped polysilicon gate electrode of the electrostatic discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.
U.S. Pat. No. 5,689,133 (Li et al.) describes an ESD protection circuit combines a split bipolar transistor with a transistor layout, which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed. The split bipolar transistor structures each combine a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snapback effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.
It is an object of this invention to provide a NMOS FET device structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, it will protect internal circuits formed on the semiconductor substrate from overstress due to excessively high voltages from an ESD voltage source.
Another object of this invention is to provide an ESD protection device that has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits.
To accomplish these and other objects an ESD protection device is formed on a semiconductor substrate. The ESD protection device connected between the junction of an input/output pad and internal circuitry with a reference voltage source. The ESD protection device prevents damage to the internal circuitry during application of an ESD voltage source to the input/output pad by conducting an ESD current uniformly from the ESD voltage source to the reference voltage source. The ESD protection device has at least one source region of a material of a first conductivity type implanted into the surface of the semiconductor substrate at a first distance and connected to the reference voltage source and at least one drain region of the material of the first conductivity type implanted into the surface the semiconductor substrate at a second distance from each other and between the plurality of source region, at a third distance from the source regions and connected to the junction of the input output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed by the deposition of a conductive material such as highly doped polycrystalline silicon upon an insulating material formed at the surface of the semiconductor substrate above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a uniformly variable length and thus the channel region has a uniformly variable length.
The ESD protection device has at least one parasitic bipolar transistor. Each parasitic bipolar transistor having a collector that is a portion of one of the drain regions, an emitter that is a portion of one of the source regions adjacent to the one drain region, and a base that is a portion of the channel region between the one drain region and the one source region. The ESD current is distributed uniformly over the channel region.
The ESD protection device also has at least one parasitic resistor formed of a bulk resistance of the semiconductor substrate and connected from the bases of the parasitic transistors connected to the reference voltage source.
The ESD protection device further optionally has a well of a material of the second conductivity type implanted into the surface of the semiconductor substrate and into which the plurality of source regions and the plurality drain regions are implanted. Or optionally, the semiconductor substrate is of the material of the second conductivity type, and the ESD protection device is formed in the surface of the semiconductor substrate.
The variable length of the gate electrodes varies from a minimum that is approximately a minimum feature size able to be formed on the semiconductor substrate to a maximum that is from approximately two times to approximately three times the minimum feature size.